The basis of most electrically alterable, non-volatile, read-only memories (EPROMs) is the ability to store charge on a high-impedance node within a semiconductor device. The presence of the stored charge must be detectable such as by affecting the characteristics of a field effect transistor. The requirement of a high-impedance storage node is dictated by the non-volatility of the device.
Typical storage nodes are: (1) floating gate conductors (such as polysilicon) or (2) non-conducting electrical traps within the device dielectric (such as insulator-insulator interfaces where one insulator is typically SiO.sub.2 and the other is another dielectric material such as Si.sub.3 N.sub.4 or Al.sub.2 O.sub.3).
In a typical "EPROM," the charge storage node is used to bias the overall MOS structure changing the threshold voltage of the device. The sensitivity of the threshold voltage of the device to changing charge level on the storage node (Q.sub.T) can be shown to be proportional to the distance from the metal gate to the traps (for a constant total insulator thickness), or dV/dQ.sub.T =(-1/.epsilon..sub.0 .epsilon..sub.1) X.sub.1.
FIG. 1 shows a cross-sectional view of a prior art composite layer dielectric charge storage node wherein a first layer 4 of dielectric having a thickness X.sub.1, on the surface silicon substrate 2, has deposited thereon a second layer 6 of a dielectric having a thickness X.sub.2. The first dielectric layer 4 may be composed of silicon dioxide, for example, and the second dielectric layer 6 may be composed of silicon nitride, for example. The layers have a conductive layer 10 on top of the layer 6 which serves as the programming gate for the composite. It has been found that electrical charges will concentrate at the interface 8 between the lower dielectric layer 4 and the upper dielectric layer 6. Charges may be injected by several prior art techniques such as avalanche injection or tunnel injection so that when the programming gate 10 is properly biased by voltage source 12 with respect to the substrate 2, charges can be added or deleted at the interface 8. When a single diffusion region 3, as in FIG. 1a is juxtaposed with the composite dielectric layers in the silicon substrate 2, a selective capacitance device may be formed. When a first and second diffused regions 5 and 7, as in FIG. 1b, are formed in the silicon substrate 2 which bound the terminal edges of the composite dielectric layers 14, a FET device having a selective transconductance is formed. FIG. 1A illustrates a first tri-storage embodiment with a single diffusion in the substrate and FIG. 1b illustrates a second tri-storage embodiment illustrating the programmable FET device with selective transconductance. The closer the charge storage node 8 is to the silicon surface 2, the less charge must be stored or removed from the charge storage node to change the state of the device. Thus, for devices with the storage node close to the silicon surface, potentially less time is required for programming the device and potentially lower voltages need be employed for that programming.
In a study of the adhesion of aluminum to silicon dioxide, a recent report by J. R. Black, "The Reaction of Al with Vitreous Silica," Paper 8.2 at the 1977 International Reliability Physics Symposium, 4/14/77, described the solid-state reaction between a layer 16 of aluminum and thermal silicon dioxide 18. EQU 4Al+3SiO.sub.2 .fwdarw.2Al.sub.2 O.sub.3 +3Si
This reaction is thermodynamically favorable at typical sintering temperatures of 400.degree.-500.degree. C. The reaction rate is controlled by solid state diffusion and results in a region 20 within the original oxide 18 extending from the metal-oxide interface 22 being converted from SiO.sub.2 to a matrix of SiO.sub.2, Al.sub.2 O.sub.3, and Si as shown in FIGS. 2a and 2b. Because the reaction is diffusion limited, excellent control of the depth of the reaction is possible. As reported by Black, typical rates of penetration range from 0.01 A/min. at 400.degree. C. to 60 A/min. at 540.degree. C.